1. Field of the Invention
The present invention relates to a self-refresh timer circuit which generates a timer period for controlling a self-refresh operation of a semiconductor memory device.
2. Related Art
A DRAM which is a typical semiconductor memory device is configured to execute self-refresh at predetermined intervals for holding data. In general, self-refresh operation is periodically performed so that a self-refresh timer circuit which generates a timer period for controlling timing of self-refresh operation is built in the DRAM. In general, when performing self-refresh, the longer the timer period is, the less the power consumption of the DRAM. For example, since low power consumption is strongly required in the DRAM for mobile use or the like, self-refresh is preferably performed by using the longest timer period as possible.
On the other hand, it is known that a data retention time of a memory cell of the DRAM has a temperature dependency, and the data retention time is decreased according to powers of temperature with increase of the temperature. Therefore, it can be assumed under the high-temperature environment that the timer period exceeds the data retention time, thereby performing an in appropriate refresh operation, even if a predetermined timer period is set so as to secure a desired data retention time in a room temperature. In order to solve the above-mentioned problem, a variety of methods for controlling the timer period according to temperature has been suggested. As a first method, for example, a configuration in which temperature measuring means is provided in the semiconductor memory device and the timer period is switched stepwise according to the measured temperature is proposed (refer to “A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme” IEEE Journal of Solid-State Circuits, Vol. 38, No. 2, February 2003). And as a second method, a configuration capable of adjusting the timer period so as to suit the data retention time by using a diode whose characteristic changes according to powers of temperature and by controlling the temperature characteristic of the diode (refer to Japanese Patent Application Laid-Open No. 2002-117671).
However, according to the above-described first method, the timer period abruptly changes at each switching temperature point when the timer period is switched stepwise according to the temperature. For example, when the timer period is switched stepwise at switching temperature points Tp1, Tp2 and Tp3 as shown in FIG. 15, control is performed according to a temperature characteristic which does not exceed a temperature characteristic Cm of the data retention time of the memory cell. In this case, since the linear temperature characteristic Cm of the data retention time is approximated by a stepwise pattern, the timer period deviates from the data retention time in the vicinity of the switching temperature points and becomes short, especially when the number of the switching temperature points decreases. Consequently, it becomes a problem that the power consumption is not sufficiently reduced. On the other hand, in order to avoid such a problem, the timer period may be controlled in a multistage stepwise pattern by setting a number of switching temperature points. But in this case, it becomes a problem that components such as a switch circuit for setting timer period to be switched, a decoder for program, a fuse and the like increase, and layout area is increased.
Further, according to the above-described second method, in order to finely control the temperature characteristic of the timer period, it is required to provide a plurality of series-connected diodes. However, considering that a forward drop voltage of the diode is approximately 0.6V, the number of diodes to be connected is restricted by a supply voltage. For example, if an operating voltage drops to 1.5V, the number of diodes to be series-connected is limited to two, and the fine control of the timer period is prevented. The configuration in which a plurality of diodes is series-connected is not preferable to a low-voltage DRAM.